1. Field of Invention
The present invention relates to a testing device and a testing module, and more particularly to a plunger and a chip-testing module applying the same.
2. Description of Related Art
Testing for integrated circuit chips (IC chips) is necessary at different stages of the semiconductor process. Each IC chip in the wafer configuration and package configuration must be tested to ensure its electrical function. Along with the enhancement and complication of chip functions, the requirements for high-speed and precise testing become more and more important.
The process of testing individual chips in the wafer configuration, called wafer sorting, includes establishing a temporary electrical contact between a chip and an automatic testing apparatus. Wafer sorting is an important test of the design and function of ICs, in order to select good IC chips before chip dicing and subsequent packaging.
Referring to FIG. 1, it shows the schematic sectional view of a conventional chip-testing module. The conventional chip-testing module 100 is suitable for being electrically connected to a tested surface TS of a chip C. The conventional chip-testing module 100 includes a plunger 110 and a probe card 120. The plunger 110 includes a body 112 with a pushing part 112a and a base part 112b. 
The probe card 120 includes a circuit board 122 and a membrane 124. The circuit board 122 has an opening 122a. The pushing part 112a of the body 112 penetrates the circuit board 122 through the opening 122a. The membrane 124 has a plurality of circuit layers 124a overlapping one another and a plurality of bumps 124b. The circuit layers 124a further include a first circuit layer L1 disposed on a first membrane surface 124c of the membrane 124, and the layers 124a also include a second circuit layer L2 disposed on a second membrane surface 124d of the membrane 124 where the second membrane surface 124d is opposite to the first membrane surface 124c. The bumps 124b are disposed on part of a pushed area PA of the second circuit layer L2, where the pushed area PA is located on the membrane 124, to contact the tested surface TS of the chip C.
The membrane 124 further has a plurality of conductive through-vias 124e (only one of which is shown) to electrically connect the circuit layers 124a. The membrane 124 further has a first dielectric layer 124f disposed on the first membrane surface 124c and covering part of the first circuit layer L1 to protect it. The membrane 124 further has a second dielectric layer 124g disposed on the second membrane surface 124d and covering part of the first circuit layer L2 to protect it.
Furthermore, the probe card 120 further includes at least one capacitor 126 disposed on the second membrane surface 124d of the membrane 124. In addition, the above-mentioned first circuit layer L1 includes a power supply circuit or a ground circuit.
The following part illustrates the process of electrically testing the chip C by using the conventional chip-testing module 100. Referring to FIGS. 1 and 2, FIG. 2 shows the schematic sectional view of the chip-testing module in FIG. 1 during performing an electrical test. After the pushed area PA of the membrane 124 is pushed by the pushing part 112a (which penetrates through the opening 122a of the circuit board 122) of the body 112 of the plunger 110 and after a pressed area SA connected to the pushed area PA of the membrane 124 is clamped between the base part 112b and the circuit board 122, the membrane 124, the circuit board 122, and the plunger 110 are fixed together to form the chip-testing module 100. In the testing process, relative displacement occurs between the chip C and the chip-testing module 100. Usually, the chip C moves perpendicularly, so that the bumps 124b of the membrane 124 contact the tested surface TS of the chip C to electrically test the chip C.
However, for the conventional chip-testing module with a membrane of high-density wiring, the connecting path of the first circuit layer is very long, resulting in an increase of its parasitic inductance value. Furthermore, the number of the signal pads on the tested surface of a chip tested by the conventional chip-testing module is limited due to the limited wiring ability of the membrane. Further, when high frequency signals are transmitted, the long connecting path of the first circuit layer increases its insertion loss, thereby reducing its transmission efficiency.